Normal view MARC view ISBD view

SYSTEM ON A CHIP VERIFICATION METHODOLOGY AND TECHNIQUES

TextPublication details: BOSTON KLUWER PUB 2001 Description: 327ISBN: 792372794Subject(s): "Digital Logic,CMOS VLSI Design"DDC classification: 621.395

Tags from this library: No tags from this library for this title. Log in to add tags.

Average rating: 0.0 (0 votes)

Holdings
Item type	Current library	Collection	Call number	Status	Date due	Barcode
General Library Books	Central Library 2nd Floor-Cup-89(Mix)	ELECTRONICS & COMMUNICATION ENGG	572.49 RAS (Browse shelf(Opens below))	Available		045975
General Library Books	Central Library 2nd Floor-Cup-89(Mix)	ELECTRONICS & COMMUNICATION ENGG	572.49 RAS (Browse shelf(Opens below))	Available		045976

	No cover image available	No cover image available	No cover image available	No cover image available	No cover image available		No cover image available	Next
	EVOLUTIONARY ALGORITHMS FOR VLSI CAD	004.22 PAS ON CHIP COMMUNICATION ARCHITECTURES SYSTEM ON CHIP INTERCONNECT	004.22 PAS ON CHIP COMMUNICATION ARCHITECTURES SYSTEM ON CHIP INTERCONNECT	572.49 RAS SYSTEM ON A CHIP VERIFICATION METHODOLOGY AND TECHNIQUES	572.49 RAS SYSTEM ON A CHIP VERIFICATION METHODOLOGY AND TECHNIQUES	621.381 5 BLE BOUNDARY SCAN TEST	621.381 5 MOU PRINCIPLES OF TESTING ELECTRONIC SYSTEMS	Next

There are no comments on this title.

to post a comment.