VLSI TEST PRINCIPLES AND ARCHITECTURES DESIGN FOR TESTABILITY (Record no. 8107)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 00404nam a2200133Ia 4500 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9789380501550 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.395 |
| 100 ## - MAIN ENTRY--AUTHOR NAME | |
| Personal name | WANG LAUNG TERNG;CHENG WEN WU;XIAOQING WEN |
| 245 #0 - TITLE STATEMENT | |
| Title | VLSI TEST PRINCIPLES AND ARCHITECTURES DESIGN FOR TESTABILITY |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication | NEW DELHI |
| Name of publisher | ELSEVIER |
| Year of publication | 2013 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | 777 |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | "Digital Logic,CMOS VLSI Design" |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | General Library Books |
| Weedout status | Lost status | Damaged status | Not for loan | Collection code | Home library | Current library | Shelving location | Date acquired | Cost, normal purchase price | Full call number | Accession Number | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ELECTRONICS & COMMUNICATION ENGG | Central Library | Central Library | Ref-5-EC-TE | 02/03/2017 | 1495.00 | 621.395 WAN | 060863 | 13/01/2018 | General Library Books |