CMOS CIRCUIT DESIGN LAYOUT AND SIMULATION (Record no. 5647)
[ view plain ]
| 000 -LEADER | |
|---|---|
| fixed length control field | 00389nam a2200133Ia 4500 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 978-8126520374 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.395 |
| 100 ## - MAIN ENTRY--AUTHOR NAME | |
| Personal name | JACOB BAKER R |
| 245 #0 - TITLE STATEMENT | |
| Title | CMOS CIRCUIT DESIGN LAYOUT AND SIMULATION |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication | NEW DELHI |
| Name of publisher | IEEE PRESS (J AND W)WILLEY INTERNSCIENCE |
| Year of publication | 2005 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | 1038 |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | "Digital Logic,CMOS VLSI Design" |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | General Library Books |
| Weedout status | Lost status | Damaged status | Not for loan | Collection code | Home library | Current library | Shelving location | Date acquired | Cost, normal purchase price | Full call number | Accession Number | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ELECTRONICS & COMMUNICATION ENGG | Central Library | Central Library | H:H7 | 09/08/2009 | 429.00 | 621.39 5 JAC | 046417 | 13/01/2018 | General Library Books | ||||
| ELECTRONICS & COMMUNICATION ENGG | Central Library | Central Library | H:H7 | 09/08/2009 | 429.00 | 621.39 5 JAC | 046418 | 13/01/2018 | General Library Books | ||||
| ELECTRONICS & COMMUNICATION ENGG | Central Library | Central Library | H:H7 | 09/08/2009 | 429.00 | 621.39 5 JAC | 046419 | 13/01/2018 | General Library Books |